This application is based upon and claims priority from prior French Patent Application No. 98-07788, filed Jun. 19, 1998, the entire disclosure of which is herein incorporated by reference.
1. Field of the Invention
The present invention relates to electronic circuits, and more specifically to circuits having a stack of alternating dielectric and conducting layers arranged on a substrate.
2. Description of Related Art
It has been found that it is necessary to ascertain the various capacitances existing between various lines of an integrated circuit (e.g., between two intersecting or parallel superposed lines or between two parallel lines in the same metallization plane). By knowing these capacitances it becomes possible to deduce the thickness of the dielectric that is arranged between the two metallized lines, and thus to monitor the process by which the integrated circuit is fabricated.
The article entitled xe2x80x9cMeasurement and Characterization of Multi-Layered Interconnect Capacitance for Deep Submicron VLSI Technologyxe2x80x9d (Proc. IEEE 1997 Int. Conference on Microelectronic Test Structures, Vol. 10, March 1997) discloses a structure for testing capacitances in an integrated circuit. The test structure includes two similar branches that are arranged between a supply terminal and ground, and each of the branches has a means for measuring current such as an NMOS transistor and a PMOS transistor arranged in series. A first portion of a first metallized line is connected to a common point between two transistors of one branch, and a second portion of the first metallized line is similarly connected to the other branch to measure the capacitance existing between the second portion of the first line and another line. The other metallized line is grounded.
In this circuit, C10 denotes the capacitance between the first portion and ground, C20 the capacitance between the second portion and ground, C23 the capacitance between the second portion and the other metallized line, Cstrayl the stray capacitance of the first branch (due to the transistors), and Cstrayr the stray capacitance of the second branch. The MOS transistors of the two branches are driven by voltage signals such that no short circuit can occur (i.e., so that the two transistors of one branch are never on at the same time). The gates of the two PMOS transistors are connected together, and the gates of the two NMOS transistors are also connected together. The current-measuring means measures the average value of the currents.
The article entitled xe2x80x9cAn on-chip, interconnect capacitance characterization method with sub-femto-farad resolutionxe2x80x9d by Chen, Sylvester, and Hu (IEEE Transactions on Semiconductor Manufacturing, Vol. 11, May 2, 1998) is similar to the article mentioned above, but proposes the use of the same current-measuring means for both of the branches. The difference between these average values is due to the charge of the capacitance that is to be measured, as given by the following equation.
xcex94I=Cxc3x97Vddxc3x97f
The capacitance can be deduced from this equation. However, in this structure, the superposition theorem does not apply so the capacitance C23 cannot be obtained. When the difference xcex94I between the currents in the two branches is taken, the following equation is obtained.
xcex94I=(C23+C10xe2x88x92C20+Cstrayrxe2x88x92Cstrayl)Vddxc3x97f
The superposition theorem does not apply because the capacitance C20 is not the same as C10 because of the presence of the metal of the third line that modifies the distribution of the field lines. Thus, this method does not make it possible to extract the term C23. Instead, all that is obtained is a sum of capacitances, which has no physical meaning and which cannot readily be utilized. When the number of metal lines increases, this sum contains additional terms and becomes unusable. Further, differences exist between the transistors of the two branches, and in particular in the drain junctions. It has actually been found that this difference can amount to a value on the order of 1 to 10%, which is difficult to measure. There may also be a discrepancy between the dimensions of the two capacitances that charge the structure. In the structure of FIG. 1 of the above-mentioned article, the metal lines 1 are supposed to be similar. However, this is only true to within the technological tolerances.
In view of these drawbacks, it is an object of the present invention to overcome the above-mentioned drawbacks and to provide a test structure having improved accuracy.
Another object of the present invention is to provide a test structure that makes it possible to measure the capacitances and overcome the problems associated with the different stray capacitances and possibilities of differences existing between the transistors of the various branches. This allows the superposition theorem to be used to deduce the values of the capacitances.
One embodiment of the present invention provides a test structure for testing a circuit of the type having a plurality of metallization planes separated by dielectric layers. The test structure includes a single current-measuring means for measuring current between a supply terminal and ground, and first and second branches for measuring capacitance between first and second metal lines. The first branch includes a first switch coupled between the current-measuring means and the first line, and a second switch coupled between the first line and ground. Similarly, the second branch includes a third switch coupled between the current-measuring means and the second line, and a fourth switch coupled between the second line and ground. In a preferred embodiment, the test structure also includes an additional branch, which is not connected to any line, for measuring stray capacitance of the switches.
Another embodiment of the present invention provides an integrated circuit that includes at least one dielectric layer, at least two metallization planes separated by the dielectric layer, and at least one test structure coupled between two terminals. The test structure includes a single current-measuring means for measuring current between the two terminals, and at least two branches for measuring the capacitance between at least two of the metal lines. Further, each of the branches includes a switch that is coupled between the current-measuring means and one of the terminals. In one preferred embodiment, each of the branches also includes another switch that is coupled between one of the lines and the one terminal.
Yet another embodiment of the present invention provides a method for testing a circuit of the type having a plurality of metallization planes separated by dielectric layers. According to the method, the capacitance between a first metal line and a second metal line is calculated by: measuring a first current that is needed to bring the first line to the voltage of a first terminal while the other lines are kept at the voltage of a second terminal, measuring a second current that is needed to bring the second line to the voltage of the first terminal while the other lines are kept at the voltage of the second terminal, and measuring a third current that is needed to bring the first and second lines to the voltage of the first terminal while the other lines are kept at the voltage of the second terminal. The measurements are performed using a single current-measuring means, and a branch having two switches in series is associated with each of the lines.
Yet another embodiment of the present invention allows calculation of other values. The height of the metal forming one of the metal lines is calculated by measuring the resistance R1 between two points of a portion with theoretical width W1, the resistance R2 between two points of another line portion with theoretical width W2, which is different from W1, the real width of a line portion differing from the theoretical width by a constant difference xcex94W regardless of the theoretical width, and by eliminating the unknown term xcex94W from the equations: R1=xcfx81xc3x97L1/H/(W1=xcex94W) and R2=xcfx81xc3x97L2+xcex94W), with p being the known resistance constant in ohm/meter associated with metal used and L being the length of the portion in question, to give H=xcfx81xc3x97(L2/R2xe2x88x92L1/R1)/(W2xe2x88x92W1). The thickness d of the dielectric separating the line from an adjacent line is calculated by using d=xcex5xc3x97L1xc3x97H/C1, xcex5 being permittivity of the material of the dielectric layer and C1 being the capacitance between the first line portion and the neighboring line from which the first portion is separated by the thickness e of the dielectric. The fabrication pitch p of the lines is calculated using p=W1+xcex94W+d and xcex94W=xcfx81xc3x97L1/H/Rxe2x88x92W2.
Still another embodiment of the present invention allows calculation of further values. A capacitance C1 between the two metal line portions with length L and width W1 in two adjacent metallization planes is measured, with the measured capacitance being equal to C1=xcex5xc3x97Lxc3x97W1/e+Cedge, with Cedge being due to edge effects that are constant regardless of the width of the line portion. A capacitance C2 between two line portions with the same length L, but with width W2, which is different from W1 and in the same metallization plane, is measured, the measured capacitance being equal to C2=xcex5xc3x97Lxc3x97W2/e+Cedge. Subtraction is used to eliminate the term Cedge and give C1xe2x88x92C2=xcex5xc3x97Lxc3x97(W1xe2x88x92W2)/e, and the value of the thickness e of the dielectric layer separating two adjacent metallization planes is deduced using e=xcex5xc3x97Lxc3x97(W1xe2x88x92W2)/(C1xe2x88x92C2).
Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the present invention, are given by way of illustration only and various modifications may naturally be performed without deviating from the present invention.